The present invention relates generally digital-to-analog (D-to-A) conversion and signal filtering, and more particularly to a combined D-to-A converter and transmit filter for a digital radio communication device.
Modern mobile communication devices often use digital modulation techniques. Digital modulation offers many advantages over analog modulation, such as greater noise immunity and greater robustness to the adverse conditions of the communication channel. Digital modulation accommodates digital error detection and correction codes that can detect and correct errors that occur in transmission. Digital modulation also allows use of various digital signal-processing techniques, such as source coding, encryption, and equalization that improves the overall performance of the communication system.
In a digital communication system, the modulating signal (i.e. the information transmitted) is represented as a time sequence of symbols or pulses. Each symbol has one of afinite number of states. There are 2n possible states where n is equal to the number of bits per symbol. The modulating signal is impressed onto a carrier waveform by varying a characteristic of the waveform. For example, in amplitude modulation, the amplitude of the carrier waveform is varied linearly with the modulating signal. In phase modulation, the phase of the waveform is varied linearly with the modulating signal. In complex modulation, also known as quadrature modulation, variations in both the amplitude and phase of the carrier waveform occur and thus create a time-varying signal vector in the two-dimensional complex plane.
FIG. 1 is a block diagram of a balanced quadrature modulator of the prior art, which is indicated generally by the numeral 10. A digital signal processor (DSP) 12 generates symbol sequences corresponding to the I and Q components of a modulating signal. The symbol sequences correspond to the real and imaginary parts of a desired complex modulation. The real part is given by the desired amplitude times the cosine of the desired phase angle. The imaginary part is given by the amplitude times the sine of the desired phase angle. Digital-to-analog (D-to-A) converters 14 convert each symbol sequence into an analog waveform, referred to as I (In-phase) and Q (Quadrature) modulating waveforms. Filters 16 remove smooth step changes in the I and Q waveforms that result from sampling and quantization. Absent filtering, the step changes in the modulating waveforms could produce undesirable spectral components in the transmitted signal that would interfere with adjacent radio channels. Filters 16 are typically low-pass filters that pass desired components of the modulating signal while suppressing higher frequency components associated with step changes in the modulating waveform. After filtering, the I and Q modulating waveforms are passed to a quadrature modulator 18, which impresses the modulating waveforms onto a carrier waveform.
It is known in the prior art that filtering may be performed using Finite Impulse Response (FIR) filters, which perform a weighted sum over a sliding window of successive symbols. Recent innovations in FIR filters are disclosed in U.S. Pat. No. 5,867,537 to Dent, which is incorporated herein by reference. The ""537 patent discloses a method of filtering a bit sequence using a shift register and resistor networks to implement the weighting coefficients of the transmit filter. Balanced I and Q signals are input to a shift register at the bit rate or a desired oversampling rate. The non-inverted and inverted outputs of each shift register stage are connected to identical first and second resistor networks. The first and second resistor networks comprise a plurality of resistors of different value representing the desired transmit filter weights. The non-inverted outputs of the shift register are used for positive weights and the inverted outputs are used for negative weights. A first group of the non-inverted and inverted outputs is connected to the first resistor network and a second complementary group of non-inverted and inverted outputs are connected to the second resistor network. Thus, the first and second resistor networks produce complementary I or Q outputs suitable for input to a balanced quadrature modulator.
One drawback to using resistive networks to perform filtering is that large resistor values are needed to implement small weighting factors. Therefore, there is a need for further improvements in FIR filters.
The present invention is a combined digital to analog converter and transmit filter for use in a quadrature modulator. According to the present invention, a transmit filter is constructed by using a combining network, such as a resistor network, connected to the taps of a shift register to provide desired tap weights. To avoid using excessively high resistor values to implement very small weights, a ladder network is used to attenuate the contribution from taps with small associated weight values. However, a ladder network may only provide a progressively increasing attenuation from one stage to the next. In order to facilitate the use of a ladder network therefore, the invention comprises, in a first aspect, sorting of the filter tap weights in order of absolute magnitude in order to determine a modified order in which the taps of the shift register must be connected to successive sections of the ladder network. In a second aspect of the invention, a filter that operates at an oversampling factor of L samples per bit period or chip period is constructed by first separating the N tap weights into L groups of N/L weights, each group corresponding to one of the L oversampling phases. A resistor network is then designed for each group of N/L taps, which are provided by a shift register of length N/L stages and clocked at the chip rate or bit rate. A higher frequency clock of L times the chip or bitrate controls progressive selection among the L resistor networks of the network that is to be connected to the shift register to provide the output for each of the L oversampling phases.
A third aspect of the invention comprises a combination of the first and second aspects described above. After separating the N tap weights into L groups of N/L weights, each group of L tap weights is sorted in order of absolute magnitude and a ladder network for each group provides progressive attenuation of the contribution from successive taps in the sorted order of each group. An array of switches is controlled by an oversampling clock of L times the chip rate or bit rate to determine which ladder network shall be driven by the shift register outputs to provide the filtered signal output for each phase.
According to a fourth aspect of the invention, when the ladder networks for two or more oversampling phases comprise the same resistor values and differ only in the order in which the taps are connected to successive ladder network sections, the filter may be simplified to a single copy of the ladder network combined with a selection switch to select the different order in which the shift register taps are connected to the ladder network for different sampling phases.
According to a fifth aspect of the invention, a balanced output from the filter may be provided for driving a balanced modulator by duplicating the resistor networks, connecting the duplicate networks to register outputs of the opposite polarity to those connected to the primary copies of the resistor networks.